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SubjectRe: [PATCH] x86: smpboot - check if we have ESR register in wakeup_secondary_cpu

* Cyrill Gorcunov <gorcunov@gmail.com> wrote:

> We should check if we have ESR register before writting to it.
>
> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
> ---
>
> Please review!
> it seems the same nit in do_boot_cpu - checking now.
>
> Index: linux-2.6.git/arch/x86/kernel/smpboot.c
> ===================================================================
> --- linux-2.6.git.orig/arch/x86/kernel/smpboot.c 2008-09-14 19:43:03.000000000 +0400
> +++ linux-2.6.git/arch/x86/kernel/smpboot.c 2008-09-14 21:49:36.000000000 +0400
> @@ -598,10 +598,12 @@ wakeup_secondary_cpu(int logical_apicid,
> * Give the other CPU some time to accept the IPI.
> */
> udelay(200);
> - maxlvt = lapic_get_maxlvt();
> - if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
> - apic_write(APIC_ESR, 0);
> - accept_status = (apic_read(APIC_ESR) & 0xEF);
> + if (APIC_INTEGRATED(apic_version[phys_apicid])) {
> + maxlvt = lapic_get_maxlvt();
> + if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
> + apic_write(APIC_ESR, 0);
> + accept_status = (apic_read(APIC_ESR) & 0xEF);
> + }
> pr_debug("NMI sent.\n");

hm, is there any non-integrated lapic that has more than 3 lvts? iirc
lvts were introduced with the integrated lapic.

Ingo


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