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SubjectRe: Kernel Summit request for Discussion of future of ATA (libata) and IDE
Hello.

Alan Cox wrote:
>>> newer controllers support the 32bit PIO data cycles. Most PCI controllers
>>> it makes no speed difference but host bus controllers (especially
>>> PIIX/ICH) really benefit.
>>>

PIIX was a pure PCI controller, IIRC. ICH is also not a "host bus"
controller, it hangs off the I/O hub bus...

>>>
>>>
>> In what way if there's no speed gain?
>>
>
> As in the numbers are the same before and after. The FIFO on the
> controller is happily hiding the extra latencies I assume.
>

Depends on the PIO mode -- in the lower ones, the prefetch reads
might really be slower than successive reads on the host bus...

>>>> supported. I couldn't track down where that bit was actually defined in
>>>> the first place, all the way back to ATA-1 it seems to be indicated as
>>>> reserved. Actually, I'm not sure why the drive cares in the first place,
>>>> it would seem like a pure host controller issue..
>>>>
>>>>
>>> It goes back before IDE into the depths of the original compaq spec. When
>>> you have a device wired basically directly to the ISA bus (original IDE)
>>>
>>>
>> ISA has only 8/16-bit data bus, so it could not have mattered
>> there...
>>
>
> Depends what a 32bit I/O looks like on the 16bit bus - timing wise.
>

Two 16-bit reads at addresses 0x1x0 and 0x1x2 with the programmed
recovery time, IIRC... It's just occured to me that in case of the
16-bit bus it should be how the drive treated the accesses at address
0x1x2 with IOCS16 asserted that could have mattered. If it honored them,
32-bit I/O could have worked even on a dumb ISA "controller", if not --
no way (unless you really had *something* between the ISA and the IDE
cable).

MBR, Sergei




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