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SubjectRe: [RFC PATCH] Fair low-latency rwlock v5


On Tue, 19 Aug 2008, Mathieu Desnoyers wrote:
>
> It strikes me that Intel has a nice (probably slow?) cmpxchg16b
> instruction on x86_64. Therefore, we could atomically update 128 bits,
> which gives the following table :

Stop this crapola.

Take a look at the rwsem thing I pointed you to. After you understand
that, come back.

The WHOLE POINT of that thing was to use only 32-bit atomics on the hot
path. Don't even start think9ing about cmpxchg16b. If you cannot do your
atomics in 32-bit, they're broken.

Please. I realize that the rwsem implementation I did is subtle. But
really. Spend the time to understand it.

Linus


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