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    SubjectRE: [PATCH 01/01][retry 1] x86: L3 cache index disable for 2.6.26
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    > > Okay, this is a simpler version that includes most of Ingo's
    > > clean-ups and style changes. It only displays the two
    > > cache index values. Is this acceptable?
    >
    > Not sure, lets ask greg. And it probably should have few lines
    > in Documentation going with it, so we know new interface is added and
    > how it looks.

    Okay, I'll add that and resubmit tomorrow.

    > > +static ssize_t show_cache_disable(struct _cpuid4_info
    > *this_leaf, char *buf)
    > > +{
    > > + int node =
    > cpu_to_node(first_cpu(this_leaf->shared_cpu_map));
    > > + struct pci_dev *dev = get_k8_northbridge(node);
    > > + ssize_t ret = 0;
    > > + int i;
    > > +
    > > + if (!this_leaf->can_disable)
    > > + return sprintf(buf, "-1");
    >
    > This should return -ERRNO, right?

    Right, thanks.

    > > + for (i = 0; i < 2; i++) {
    > > + unsigned int reg = 0;
    > > +
    > > + pci_read_config_dword(dev, 0x1BC + i * 4, &reg);
    > > +
    > > + ret += sprintf(buf, "%s %x\t", buf, reg);
    > > + }
    > > + ret += sprintf(buf,"%s\n", buf);
    >
    > So you print "buf" few times? Why? And you use both \t and \n
    > as deliminer...

    I'm printing the values of the two config registers into
    the string buffer, separated by tabs, and terminated by
    an EOL. Is there a prefered way to do that instead of
    what I have?

    -Mark Langsdorf
    Operating System Research Center
    AMD



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