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    Subject[PATCH 02/24] x86: apic_*.c: Add description to AMD's extended LVT functions
    Date
    Signed-off-by: Robert Richter <robert.richter@amd.com>
    ---
    arch/x86/kernel/apic_32.c | 3 +++
    arch/x86/kernel/apic_64.c | 3 +++
    2 files changed, 6 insertions(+), 0 deletions(-)

    diff --git a/arch/x86/kernel/apic_32.c b/arch/x86/kernel/apic_32.c
    index d6c8983..fad94b0 100644
    --- a/arch/x86/kernel/apic_32.c
    +++ b/arch/x86/kernel/apic_32.c
    @@ -646,6 +646,9 @@ int setup_profiling_timer(unsigned int multiplier)
    *
    * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
    * MCE interrupts are supported. Thus MCE offset must be set to 0.
    + *
    + * If mask=1, the LVT entry does not generate interrupts while mask=0
    + * enables the vector. See also the BKDGs.
    */

    #define APIC_EILVT_LVTOFF_MCE 0
    diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c
    index 7f1f030..42bf69f 100644
    --- a/arch/x86/kernel/apic_64.c
    +++ b/arch/x86/kernel/apic_64.c
    @@ -205,6 +205,9 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
    *
    * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
    * MCE interrupts are supported. Thus MCE offset must be set to 0.
    + *
    + * If mask=1, the LVT entry does not generate interrupts while mask=0
    + * enables the vector. See also the BKDGs.
    */

    #define APIC_EILVT_LVTOFF_MCE 0
    --
    1.5.5.4



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