Messages in this thread | | | From | Roland Dreier <> | Subject | Re: Can Linux control PCIe Transaction Layer Packet creation, when writing to a region pointed to by Base Address Register | Date | Mon, 09 Jun 2008 12:42:38 -0700 |
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> Any thoughts or suggestions of how to ensure a buffer's data is > transferred from the driver to the PCIe card in a single TLP (where > the intended payload size is less than the max payload value in > Device Control register of the PCI register space)?
If you are doing MMIO (memory-mapped IO, that is, the CPU is using write operations to write to a memory-mapped PCI BAR), then you probably cannot ensure that the data goes into a single PCIe packet. I think the best you can do is map the PCI memory into the CPU's address space with write combining (WC) enabled (see ioremap_wc() in recent kernels), which is likely to generate larger bursts if possible.
- R.
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