Messages in this thread | | | Date | Thu, 19 Jun 2008 08:42:53 -0400 | From | Mathieu Desnoyers <> | Subject | Re: [PATCH]: Sparc64 immediate values |
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Hi David,
I'm picking this patch up in my LTTng patchset for testing.
Thanks,
Mathieu
* David Miller (davem@davemloft.net) wrote: > From: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> > Date: Tue, 13 May 2008 08:36:15 -0400 > > > However, it does not protect from having a thread preempted in the > > middle of this instruction sequence and therefore to see incoherent > > values. > > Yes, that makes such schemes unworkable, how hum... > > > Are there non-maskable interrupts on sparc64 ? > > Yes, and no. When the PSTATE_IE bit is cleared in the > processor state register, no interrupts whatsoever are > recognized by the processor. This is off only during > trap entry/exit sequences, and some other special bits > of code. > > > The one thing we could do to allow such updates without using > > stop_machine is to create something similar to the read seqlock using > > immediate values. > > Yes I saw such suggestions in the comments of the immediate code, > you don't have to describe such things all over again. > > Doing something so heavy like this in the "fast path" is completely > pointless in my opinion. > > Better to keep brainstorming on a scheme that works without adding any > instructions to the immediate load sequence. If you add instructions, > fetching the instructions themselves become just as expensive, if not > moreso, than the load we are eliminating.
-- Mathieu Desnoyers OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F BA06 3F25 A8FE 3BAE 9A68
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