lkml.org 
[lkml]   [2008]   [May]   [3]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: HELP: Is writeq an atomic operation??
From
Date

On Fri, 2008-05-02 at 15:46 -0700, Roland Dreier wrote:
> > Is a 64bit write to MMIO registers an atomic operation when using the
> > writeq API?
> >
> > My concern is when I send 64bit data via writeq, will it be sent out as
> > two 32 bit writes? If so, is it possible that another CPU be sending
> > the data at the same time. Meaning can I write the 1st 32bit data from
> > CPU-A, meanwhile CPU-B is writing his 32bit data at the same time, and
> > CPU-A didn't complete the full 64bit in one shot. If this could occur,
> > is there an API that I can use to make sure the entire data sent in one
> > atomic operation?
>
> I don't have an authoritative answer, but I can say that I coded
> drivers/infiniband/hw/mthca and .../mlx4 assuming that writeq() is
> atomic in the sense that you say, and no one has reported any problems.
>
> But I'm sure no one has stressed the drivers on 64-bit mips or anything
> unusual like that.

Surely only on 64 bits archs right ?

Ben.




\
 
 \ /
  Last update: 2008-05-04 00:41    [W:0.078 / U:0.224 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site