Messages in this thread | | | Date | Tue, 20 May 2008 16:38:08 -0500 | From | Scott Wood <> | Subject | Re: [PATCH] [POWERPC] Improve (in|out)_beXX() asm code |
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Benjamin Herrenschmidt wrote: > On Tue, 2008-05-20 at 13:40 -0700, Trent Piepho wrote: >> There was some discussion on a Freescale list if the powerpc I/O accessors >> should be strictly ordered w.r.t. normal memory. Currently they are not. It >> does not appear as if any other architecture's I/O accessors are strictly >> ordered in this manner. memory-barriers.txt explicitly states that the I/O >> space (inb, outw, etc.) are NOT strictly ordered w.r.t. normal memory >> accesses and it's implied the other I/O accessors (e.g., writel) are the same. >> >> However, it is somewhat harder to program for this model, and there are almost >> certainly a number of drivers using coherent DMA which have subtle bugs because >> the do not include the necessary barriers. >> >> But clearly and change to this would be a subject for a different patch. > > The current accessors should provide all the necessary ordering > guarantees...
It looks like we rely on -fno-strict-aliasing to prevent reordering ordinary memory accesses (such as to DMA descriptors) past the I/O access. It won't prevent reordering of memory reads around an I/O read, though, which could be a problem if the I/O read result determines the validity of the DMA buffer. IMHO, a memory clobber would be better.
-Scott
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