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    SubjectRe: [patch] x86, voyager: fix ioremap_nocache()
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    On Mon, 2008-04-28 at 07:10 -0700, Arjan van de Ven wrote:
    > On Sun, 27 Apr 2008 18:39:24 -0400
    > Jeff Garzik <jeff@garzik.org> wrote:
    >
    > > James Bottomley wrote:
    > > > Here's another piece of the x86 API that's designed to be cached.
    > > > The dma_declare_coherent_memory() usually represents behind bridge
    > > > memory that's fully participatory in the coherence model.
    > > >
    > > > Making it uncached damages the utility of this memory because doing
    > > > cacheline sized burst cycles when needed to it is far faster than
    > > > individual byte/word/quad writes.
    > > >
    > > > Signed-off-by: James Bottomley
    > > > <James.Bottomley@HansenPartnership.com>
    > > >
    > > > ---
    > > >
    > > > diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
    > > > index 388b113..df83ffd 100644
    > > > --- a/arch/x86/kernel/pci-dma.c
    > > > +++ b/arch/x86/kernel/pci-dma.c
    > > > @@ -214,7 +214,7 @@ int dma_declare_coherent_memory(struct device
    > > > *dev, dma_addr_t bus_addr,
    > > > /* FIXME: this routine just ignores
    > > > DMA_MEMORY_INCLUDES_CHILDREN */
    > > > - mem_base = ioremap(bus_addr, size);
    > > > + mem_base = ioremap_cache(bus_addr, size);
    > > > if (!mem_base)
    > > > goto out;
    >
    > this patch patch is likely broken on x86; or rather, anyone who uses it is...
    > thinking you can find cache coherent memory on a PCI or similar bus that is actually
    > cachable... keep dreaming. (for now; there's talk about extending PCI)

    No ... it works for me, and caching is a performance advantage for me
    too. The only current consumer of this API is the NCR_Q720 SCSI card
    which keeps a bunch of cacheable memory remote across the MCA bus.

    If you think about it logically, most busses are second citizens in the
    caching hierarchy: they really only get to force a flush and invalidate
    of the CPU cache line rather than being fully participatory in the
    coherence protocol. However, even being second class is enough of a
    speed up on slow busses because it allows bursting of the cache line for
    the bus transfers.

    The other consumers are SoC embedded ... so yes, perhaps I should ask
    about this on linux-arch.

    James




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