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    SubjectRe: Why /proc/cpuinfo doesn't print L1,L2,L3 caches?
    On Tue, Mar 25, 2008 at 10:39:39PM +0100, J.C. Pizarro wrote:

    > How can i know what hw-caches use the processors?
    > The current kernel doesn't know well what hw-caches uses.
    >
    > The good proposal is by example (the data below are not real):
    > * In old AMD Athlon64:
    >
    > cache L1 : 64 KiB I + 64 KiB D, 64 B line, direct way, ...
    > cache L2 : 512 KiB I+D-shared, exclusive, 128 associative way, ...
    > cache L3 : none
    >
    > * In Intel Core Duo:
    > processor : 0
    > cache L1 : 32 KiB I + 32 KiB D, 64 B line, direct way, ...
    > cache L2 : 2048 KiB Cores-shared, inclusive, 128 associative way, ...
    > cache L3 : none
    >
    > processor : 1
    > cache L1 : 32 KiB I + 32 KiB D, 64 B line, direct way, ...
    > cache L2 : 2048 KiB cores-shared, inclusive, 128 associative way, ...
    > cache L3 : none
    >
    > * In Quad:
    > processor : 0
    > cache L1 : 32 KiB I + 32 KiB D, 64 B line, direct way, ...
    > cache L2 : 2048+2048 KiB pair-cores-shared, inclusive, 128
    > associative way, ...
    > cache L3 : none
    > ...
    > processor : 3
    > cache L1 : 32 KiB I + 32 KiB D, 64 B line, direct way, ...
    > cache L2 : 2048+2048 KiB pair-cores-shared, inclusive, 128
    > associative way, ...
    > cache L3 : none

    See x86info. http://www.codemonkey.org.uk/projects/x86info/

    Dave

    --
    http://www.codemonkey.org.uk


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