lkml.org 
[lkml]   [2008]   [Mar]   [25]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectWhy /proc/cpuinfo doesn't print L1,L2,L3 caches?
$ cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 15
model : 47
model name : AMD Athlon(tm) 64 Processor 3200+
...
cache size : 512 KB
...

The cache size is currently misinformed. It's not the real size because
it's 64+64+512 KiB = 640 KiB, not 512 KB.

How can i know what hw-caches use the processors?
The current kernel doesn't know well what hw-caches uses.

The good proposal is by example (the data below are not real):
* In old AMD Athlon64:

cache L1 : 64 KiB I + 64 KiB D, 64 B line, direct way, ...
cache L2 : 512 KiB I+D-shared, exclusive, 128 associative way, ...
cache L3 : none

* In Intel Core Duo:
processor : 0
cache L1 : 32 KiB I + 32 KiB D, 64 B line, direct way, ...
cache L2 : 2048 KiB Cores-shared, inclusive, 128 associative way, ...
cache L3 : none

processor : 1
cache L1 : 32 KiB I + 32 KiB D, 64 B line, direct way, ...
cache L2 : 2048 KiB cores-shared, inclusive, 128 associative way, ...
cache L3 : none

* In Quad:
processor : 0
cache L1 : 32 KiB I + 32 KiB D, 64 B line, direct way, ...
cache L2 : 2048+2048 KiB pair-cores-shared, inclusive, 128
associative way, ...
cache L3 : none
...
processor : 3
cache L1 : 32 KiB I + 32 KiB D, 64 B line, direct way, ...
cache L2 : 2048+2048 KiB pair-cores-shared, inclusive, 128
associative way, ...
cache L3 : none

It above is an example, put your symbols to /proc/cpuinfo in a
convenient manner.

Good bye ;)


\
 
 \ /
  Last update: 2008-03-25 22:49    [from the cache]
©2003-2011 Jasper Spaans