[lkml]   [2008]   [Mar]   [25]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRE: [11/14] vcompound: Fallbacks for order 1 stack allocations on IA64 and x86
    > I thought the only pinned TLB entry was for the per cpu area? How does it 
    > pin the TLB? The expectation is that a single TLB covers the complete
    > stack area? Is that a feature of fault handling?

    Pinning TLB entries on ia64 is done using TR registers with the "itr"
    instruction. Currently we have the following pinned mappings:

    itr[0] : maps kernel code. 64MB page at virtual 0xA000000100000000
    dtr[1] : maps kernel data. 64MB page at virtual 0xA000000100000000

    itr[1] : maps PAL code as required by architecture

    dtr[1] : maps an area of region 7 that spans kernel stack
    page size is kernel granule size (default 16M).
    This mapping needs to be reset on a context switch
    where we move to a stack in a different granule.

    We used to used dtr[2] to map the 64K per-cpu area at 0xFFFFFFFFFFFF0000
    but Ken Chen found that performance was better to use a dynamically
    inserted DTC entry from the Alt-TLB miss handler which allows this
    entry in the TLB to be available for generic use (on most processor


     \ /
      Last update: 2008-03-25 20:19    [W:0.024 / U:4.656 seconds]
    ©2003-2017 Jasper Spaans. hosted at Digital OceanAdvertise on this site