Messages in this thread | | | Subject | RE: [11/14] vcompound: Fallbacks for order 1 stack allocations on IA64 and x86 | Date | Tue, 25 Mar 2008 12:09:49 -0700 | From | "Luck, Tony" <> |
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> I thought the only pinned TLB entry was for the per cpu area? How does it > pin the TLB? The expectation is that a single TLB covers the complete > stack area? Is that a feature of fault handling?
Pinning TLB entries on ia64 is done using TR registers with the "itr" instruction. Currently we have the following pinned mappings:
itr[0] : maps kernel code. 64MB page at virtual 0xA000000100000000 dtr[1] : maps kernel data. 64MB page at virtual 0xA000000100000000
itr[1] : maps PAL code as required by architecture
dtr[1] : maps an area of region 7 that spans kernel stack page size is kernel granule size (default 16M). This mapping needs to be reset on a context switch where we move to a stack in a different granule.
We used to used dtr[2] to map the 64K per-cpu area at 0xFFFFFFFFFFFF0000 but Ken Chen found that performance was better to use a dynamically inserted DTC entry from the Alt-TLB miss handler which allows this entry in the TLB to be available for generic use (on most processor models).
-Tony
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