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SubjectRe: [PATCH 1/3 v3] dma: document dma_{un}map_{single|sg}_attrs() interface
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On Thursday, March 13, 2008 10:21 pm Grant Grundler wrote:
> > What if something is writing to a device?
>
> aka MMIO writes. Not defined and in general unrelated. AFAIK, no
> version of PCI has ordering rules for traffic going in opposite
> directions. I'm 99% sure about this but haven't reviewed any
> PCI docs in about 2 years.

Yeah, afaik mmio traffic will be unaffected. It's travelling in the other
direction and subject to different ordering constraints.

> On a related note, I always think of MSI/MSI-X as DMA Writes.
> Michael's got me thinking we need to explicitly state that.
> In "normal" use, the device will not issue an MSI until after
> the "completion DMA write" has been issued and thus the MSI/MSI-X
> transactions are NOT subject to the ordering requirement...but
> that's not exactly true. We don't want the MSI to ever
> pass the "completion DMA write".
>
> Do we need to state the platform interconnect can NOT allow
> successive DMA writes to pass the ordered DMA writes?
> Or state MSI DMA writes are implied to be to an "ordered DMA region"?
> Both statements?

Yeah, I've always thought of MSIs the same way. The platform really should
ensure that MSIs have this barrier bit set (regular interrupts on Altix are
actually DMAs as well, and have the barrier bit set), either these docs or
the MSI docs should probably indicate as much. That could be done as a
separate patch though...

Jesse


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