Messages in this thread |  | | From | David Brownell <> | | Subject | Re: [spi-devel-general] atmel_spi clock polarity | | Date | Mon, 18 Feb 2008 11:57:56 -0800 |
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On Monday 18 February 2008, Atsushi Nemoto wrote: > IIRC the clock state follows > CSRn.CPOL just before the real transfer.
No ... clock state should be valid *before* chipselect goes active. So I'm thinking the patch from Haavard is likely the right change.
> Like this (previous transfer > was MODE 0, new transfer is MODE 3): > > T0 T1 T2 > > CS ~~~|________________________________________________
So at T0, some chip is selected (and never deselected) ...
> > CLK ______________________|~|___|~~~|___|~~~|___|~~~|___
... and at T1 CPOL is changed?? That's wrong. There should never be a partial clock period while a chipselect is active. While it's inactive, sure -- no chip should care.
> > SO ~~~~~~~~~~~~~~~~~~~~~~~~~~|___|~~~|___|~~~|___|~~~|_ > MSB > > T0-T1 was relatively longer then T1-T2. I suppose T1 is not the > point of updating MR register, but the point of starting DMA transfer. >
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