Messages in this thread | | | Date | Thu, 04 Dec 2008 16:37:41 -0800 (PST) | Subject | Re: [patch 2/3] performance counters: documentation | From | David Miller <> |
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From: Paul Mackerras <paulus@samba.org> Date: Fri, 5 Dec 2008 11:33:31 +1100
> This is going to be a huge problem, at least on powerpc, because it > means that the kernel will have to know which events can be counted on > which counters and what values need to be put in the control registers > to select them.
Sparc64 is the same.
> The situation will be even worse with POWER5 and POWER6, where the > event selection logic is very complex, with multiple layers of > multiplexers. I really really don't want the kernel to have to know > about all that.
Niagara2 has deep multiplexing and sub-event masking too.
I really appreciated how perfmon kept all of those details in userspace.
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