Messages in this thread | | | From | Herbert Xu <> | Subject | Re: [RFC PATCH crypto] AES: Add support to Intel AES-NI instructions | Date | Wed, 17 Dec 2008 12:26:17 +1100 |
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Huang Ying <ying.huang@intel.com> wrote: > > f. if TS is clear, then use x86_64 implementation. Otherwise if > user-space has touched the FPU, we save the state, if not then simply > clear TS.
Well I'd rather avoid using the x86_64 implementation ever because unless the chip guys have really screwed up we should be looking at a difference of at least a factor of 10.
BTW I wasn't very clear in the original email. You'd only do the asynchronous operation for CBC/ECB. For the simple AES case I suppose we'll just have to stick to the x86_64 fallback. This'll really suck for disk encryption but I guess you could always add an LRW/XTS mode to your code.
Cheers, -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} <herbert@gondor.apana.org.au> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
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