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Subject[patch 2/3] x86: Add smp_mb() before sending INVALIDATE_TLB_VECTOR
On x86, x2apic mode accesses for sending IPI's don't have serializing
semantics. If the IPI receiver refers(in lock-free fashion) to some memory setup
by the sender, the need for smp_mb() before sending the IPI becomes critical in
x2apic mode.

Add the smp_mb() in native_flush_tlb_others() before sending the IPI.

Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
---
Index: linux-2.6.git/arch/x86/kernel/tlb_32.c
===================================================================
--- linux-2.6.git.orig/arch/x86/kernel/tlb_32.c 2008-10-13 10:04:12.000000000 -0700
+++ linux-2.6.git/arch/x86/kernel/tlb_32.c 2008-11-04 10:01:16.000000000 -0800
@@ -154,6 +154,12 @@
flush_mm = mm;
flush_va = va;
cpus_or(flush_cpumask, cpumask, flush_cpumask);
+
+ /*
+ * Make the above memory operations globally visible before
+ * sending the IPI.
+ */
+ smp_mb();
/*
* We have to send the IPI only to
* CPUs affected.
Index: linux-2.6.git/arch/x86/kernel/tlb_64.c
===================================================================
--- linux-2.6.git.orig/arch/x86/kernel/tlb_64.c 2008-10-31 11:15:11.000000000 -0700
+++ linux-2.6.git/arch/x86/kernel/tlb_64.c 2008-11-04 10:01:31.000000000 -0800
@@ -183,6 +183,11 @@
cpus_or(f->flush_cpumask, cpumask, f->flush_cpumask);

/*
+ * Make the above memory operations globally visible before
+ * sending the IPI.
+ */
+ smp_mb();
+ /*
* We have to send the IPI only to
* CPUs affected.
*/
--



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