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    Subject[PATCH 01/16] Blackfin SPI Driver: ensure cache coherency before doing DMA
    Date
    From: Vitja Makarov <vitja.makarov@gmail.com>

    flush or invalidate caches before doing DMA transfer, if needed.

    Signed-off-by: Vitja Makarov <vitja.makarov@gmail.com>
    Signed-off-by: Bryan Wu <cooloney@kernel.org>
    ---
    drivers/spi/spi_bfin5xx.c | 16 ++++++++++++++++
    1 files changed, 16 insertions(+), 0 deletions(-)

    diff --git a/drivers/spi/spi_bfin5xx.c b/drivers/spi/spi_bfin5xx.c
    index 7fea3cf..e9b7366 100644
    --- a/drivers/spi/spi_bfin5xx.c
    +++ b/drivers/spi/spi_bfin5xx.c
    @@ -26,6 +26,10 @@
    #include <asm/portmux.h>
    #include <asm/bfin5xx_spi.h>

    +/* reserved_mem_dcache_on and cache friends */
    +#include <asm/cplbinit.h>
    +#include <asm/cacheflush.h>
    +
    #define DRV_NAME "bfin-spi"
    #define DRV_AUTHOR "Bryan Wu, Luke Yang"
    #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
    @@ -795,6 +799,12 @@ static void pump_transfers(unsigned long data)
    /* set transfer mode, and enable SPI */
    dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");

    + /* invalidate caches, if needed */
    + if (bfin_addr_dcachable((unsigned long) drv_data->rx))
    + invalidate_dcache_range((unsigned long) drv_data->rx,
    + (unsigned long) (drv_data->rx +
    + drv_data->len));
    +
    /* clear tx reg soformer data is not shifted out */
    write_TDBR(drv_data, 0xFFFF);

    @@ -815,6 +825,12 @@ static void pump_transfers(unsigned long data)
    } else if (drv_data->tx != NULL) {
    dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");

    + /* flush caches, if needed */
    + if (bfin_addr_dcachable((unsigned long) drv_data->tx))
    + flush_dcache_range((unsigned long) drv_data->tx,
    + (unsigned long) (drv_data->tx +
    + drv_data->len));
    +
    /* start dma */
    dma_enable_irq(drv_data->dma_channel);
    dma_config = (RESTART | dma_width | DI_EN);
    --
    1.5.6.3

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