Messages in this thread | | | Date | Mon, 17 Nov 2008 09:46:55 +0800 | From | "Zhao, Yu" <> | Subject | Re: [PATCH 0/16 v6] PCI: Linux kernel SR-IOV support |
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Avi Kivity wrote: > Anthony Liguori wrote: >> I don't think it's established that PV/VF will have less latency than >> using virtio-net. virtio-net requires a world switch to send a group >> of packets. The cost of this (if it stays in kernel) is only a few >> thousand cycles on the most modern processors. >> >> Using VT-d means that for every DMA fetch that misses in the IOTLB, >> you potentially have to do four memory fetches to main memory. There >> will be additional packet latency using VT-d compared to native, it's >> just not known how much at this time. > > If the IOTLB has intermediate TLB entries like the processor, we're > talking just one or two fetches. That's a lot less than the cacheline > bouncing that virtio and kvm interrupt injection incur right now. >
The PCI SIG Address Translation Service (ATS) specifies a way that uses an Address Translation Cache (ATC) in the Endpoint to reduce the latency.
The Linux kernel support for ATS capability will come soon.
Thanks, Yu
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