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SubjectRe: [PATCH] SiS55x, another x86 CPU
On Mon, 13 Oct 2008, Andi Kleen wrote:

> Hans Schou <> writes:
>> flags : fpu tsc cx8 mmx
>> Instruction and data cache is 8KB each it says in the datasheet. I'm
>> not sure but it does not look like it is written in dmesg.
>> ACPI sleep supports S1 S2 S3 S4 S5.
>> CPU power states supports C0 C1 C2 C3.
>> See attachment. (I hope it gets here!)
> Your attachment seems to be windows line end damaged.

Strange, Pine usually do it right with file attachments.
(what is "windows line end damaged"?)

> Also the changes are so small that it's not worth adding a CONFIG
> for it. Just add it unconditionally.

I was not trying to invent anything. It is almost a copy of the UMC
CPU, except that it is 586 code.

> And hardcoding the cache size for all of SiS seems a bit extreme.
> What happens when SiS ever brings out another part with different
> caches? Ideally figure out some way to detect this particular CPU
> and only use 8 KB only for that. Alternatively ignore it (there's
> nothing really in the kernel that uses the cache sizes anyways)

In that case the cache could be deleted.

One annoying thing is that the "model name" in /proc/cpuinfo is
written as "00/55" instead of "SiS55x" when the CPU is not detected.

The worst problem is that an unknown CPU writes:
printk(KERN_ERR "CPU: Your system may be unstable.\n");
and the SiS55x is not unstable. Not until now at least and it has been
on the market for 5 years.

Maybe the message could be changed to something less catastrophic when
CPU is unknown.

So, many solutions could be be better than the one there is now.
And if the new solution will be usefull for other unknown CPU's it
will be even better.


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