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    SubjectRe: [PATCH]PCIE ASPM support - takes 3
    Pavel Machek wrote:
    > Hi!
    >> v3->v2, fixed the issues Matthew Wilcox raised.
    >> PCI Express ASPM defines a protocol for PCI Express components in the D0
    >> state to reduce Link power by placing their Links into a low power state
    >> and instructing the other end of the Link to do likewise. This
    >> capability allows hardware-autonomous, dynamic Link power reduction
    >> beyond what is achievable by software-only controlled power management.
    >> However, The device should be configured by software appropriately.
    >> Enabling ASPM will save power, but will introduce device latency.
    > How big is the latency? 1msec? 10msec? 100usec?

    the latency is different for each device but the timing is negotiated and the
    pci-e spec lists possible timings that can be used. The maximum is (I think...)
    64usec but can be as low as 1 or 2 usec.


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