Messages in this thread | | | Date | Thu, 24 Jan 2008 13:36:31 -0800 | From | "H. Peter Anvin" <> | Subject | Re: [patch 0/4] x86: PAT followup - Incremental changes and bug fixes |
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Eric W. Biederman wrote: >> >> | WB WT WC UC >> ---+--------------- >> WB | WB WT WC UC >> WT | WT WT UC UC >> WC | WC UC WC UC >> UC | UC UC UC UC >> >> With the current PAT encoding: >> >> WB = 00 >> WT = 01 >> WC = 10 >> UC = 11 >> >> ... this is simply a bitwise OR. This makes sense, since one of the bits denies >> delaying writes (WT, UC), and the other denies delaying reads (WC, UC). > > Almost. There is a specific case and important where MTRR UC + page table WC == WC. > > But yes. For ioremap where we are WB + MTRR == MTRR we need to request the > same attributes as the e820 map, to get the attribute checking correct. >
True; however, that shouldn't be followed for the case of conflicting attempts at mapping.
Now, I *believe* it is safe to have some mappings UC and some WC. This is also something to keep in mind (there are legitimate applications for that particular form of aliasing, too.) If so, we may not want to thump at those.
-hpa
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