Messages in this thread | | | Date | Sat, 12 Jan 2008 20:36:59 -0500 | From | Tony Camuso <> | Subject | Re: [Patch v2] Make PCI extended config space (MMCONFIG) a driver opt-in |
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Thanks, Arjan.
The problem we have been experiencing has to do with Northbridges, not with devices.
As far as the device is concerned, after the Northbridge translates the config access into PCI bus cycles, the device has no idea what mechanism drove the Northbridge to the translation.
That is to say, the device does not know whether the config cycle on the bus was caused by an MMCONFIG cycle or a legacy Port IO cycle delivered to the Northbridge.
In systems that had Northbridges that did not respond correctly to MMCONFIG cycles, like the AMD 8132, we (HP & RH) were blacklisting whole platforms to limit them to Port IO PCI config.
However, when platforms emerged using both legacy PCI and PCI express, the platforms that were limited to Port IO config cycles were not express compliant, since the express spec requires the platform to be able to address the full 4096 byte region of config space to be considered express-compliant.
The patch I devised concerned itself with Northbridges and separated MMCONFIG-compliant buses from those that could not handle MMCONFIG.
Therefore, the express bus in the platform could happily employ MMCONFIG to access the entire 4K region, while the legacy bus with the non-compliant Northbridge could be restricted to Port IO config.
However, even with my patch, the problem remained where devices requiring large displacements could overlap the BIOS-mapped MMCONFIG region. In such a situation, where the bus has passed the MMCONFIG test, the MMCONFIG region can get doubly mapped by bus-sizing code, causing the system to hang.
The remedy proposed by Loic and implemented by Ivan is actually quite elegant, in that it addresses all these problems quite effectively while eliminating a ration of specialized and somewhat obscure code.
In my humble opinion, Port IO config access is here to stay, having been defined as an architected mechanism in the PCI 2.1 spec.
This is most especially true for x86.
In other words, for x86, I don't think we need to worry about Port IO config access ever going away at all.
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