Messages in this thread | | | Date | Fri, 28 Sep 2007 09:15:06 -0700 (PDT) | From | Linus Torvalds <> | Subject | Re: [patch] x86: improved memory barrier implementation |
| |
On Fri, 28 Sep 2007, Alan Cox wrote: > > However > - You've not shown the patch has any performance gain
It would be nice to see this.
> - You've probably broken Pentium Pro
Probably not a big deal, but yeah, we should have that broken-ppro option.
> - and for modern processors its still not remotely clear your patch is > correct because of NT stores.
This one I disagree with. The *old* code doesn't honor NT stores *either*.
The fact is, if you use NT stores and then depend on ordering, it has nothing what-so-ever to do with spinlocks or smp_[rw]mb. You need to use the DMA barriers (ie the non-smp ones).
The non-temporal stores should be basically considered to be "IO", not any normal memory operation.
Linus - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |