Messages in this thread Patch in this message | | | Date | Fri, 20 Jul 2007 19:15:32 +0200 | From | "Andreas Herrmann" <> | Subject | Re: [patches] [PATCH] [17/58] i386: Add L3 cache support to AMD CPUID4 emulation |
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I think, Joachim's patch (sent to patches@x86-64.org on June 14) should be added as well. I have attached his patch below.
Regards,
Andreas
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This will allow the size field to be reported for all values instead of a handful and also fills the shard_cpu_map with meaning full value.
Signed-off-by: Joachim Deguara <joachim.deguara@amd.com> Index: kernel/arch/i386/kernel/cpu/intel_cacheinfo.c =================================================================== --- kernel.orig/arch/i386/kernel/cpu/intel_cacheinfo.c +++ kernel/arch/i386/kernel/cpu/intel_cacheinfo.c @@ -224,12 +224,7 @@ static void __cpuinit amd_cpuid4(int lea assoc = l3.assoc; line_size = l3.line_size; lines_per_tag = l3.lines_per_tag; - switch (l3.size_encoded) { - case 4: size_in_kb = 2 * 1024; break; - case 8: size_in_kb = 4 * 1024; break; - case 12: size_in_kb = 6 * 1024; break; - default: size_in_kb = 0; break; - } + size_in_kb = l3.size_encoded * 512; break; default: return; @@ -238,7 +233,10 @@ static void __cpuinit amd_cpuid4(int lea eax->split.is_self_initializing = 1; eax->split.type = types[leaf]; eax->split.level = levels[leaf]; - eax->split.num_threads_sharing = 0; + if (leaf == 3) + eax->split.num_threads_sharing = current_cpu_data.x86_max_cores - 1; + else + eax->split.num_threads_sharing = 0; eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1; _______________________________________________ patches mailing list patches@x86-64.org https://www.x86-64.org/mailman/listinfo/patches
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