| Date | Fri, 20 Jul 2007 19:00:49 +0200 | From | "Andreas Herrmann" <> | Subject | Re: [patches] [PATCH] [17/58] i386: Add L3 cache support to AMD CPUID4 emulation |
| |
On Thu, Jul 19, 2007 at 11:55:02AM +0200, Andi Kleen wrote: > > With that an L3 cache is correctly reported in the cache information in /sys > > With fixes from Andreas Herrmann and Dean Gaudet > > Signed-off-by: Andi Kleen <ak@suse.de> > > --- > arch/i386/kernel/cpu/intel_cacheinfo.c | 74 ++++++++++++++++++++++++--------- > arch/x86_64/kernel/setup.c | 7 ++- > 2 files changed, 60 insertions(+), 21 deletions(-)
Reporting of L3 cache information should also be enabled in 32bit mode.
Regards,
Andreas --
Enable reporting of L3 cache info in 32 bit mode for family 0x10.
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c index 6f47eee..815a5f0 100644 --- a/arch/i386/kernel/cpu/amd.c +++ b/arch/i386/kernel/cpu/amd.c @@ -272,8 +272,12 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) } #endif - if (cpuid_eax(0x80000000) >= 0x80000006) - num_cache_leaves = 3; + if (cpuid_eax(0x80000000) >= 0x80000006) { + if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000)) + num_cache_leaves = 4; + else + num_cache_leaves = 3; + } if (amd_apic_timer_broken()) set_bit(X86_FEATURE_LAPIC_TIMER_BROKEN, c->x86_capability);
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
|