Messages in this thread | | | Date | Fri, 22 Jun 2007 22:30:10 -0400 | From | "Albert Cahalan" <> | Subject | Re: JIT emulator needs |
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On 6/22/07, Arjan van de Ven <arjan@infradead.org> wrote:
> > > > > and these methods also destroy yourself on any machine with a looser > > > > > cache coherency between I and D-cache.... > > > > > > > > > > for all but x86 you pretty much have to do the mprotect() between the > > > > > two states to deal with the cache flushing properly... > > > > > > > > If the instructions to force data write-back and/or to > > > > invalidate the instruction cache are priveleged, yes. > > > > AFAIK, only ARM is that lame. > > > > > > and your program executes this on all the cpus in the system? > > no I meant that you had to call your userspace instruction on all cpus, > so on all-but-arm (from the Intel side I know IA64 needs such a flush, > but I'm pretty sure PPC does too)
I understood.
AFAIK, it is common to propagate this via a special bus cycle. Section 5.1.5.2.1 of the PowerPC manual states that this is so. Secion 5.1.5.2 lists the requirements for both uniprocessor and multiprocessor. Note that Linux uses the coherent memory model for PowerPC SMP. See also the "icbi" instruction description, where the use of an address-only broadcast is mentioned.
> > I don't recall seeing such code in the libgcc tranpoline > > setup for PowerPC. Either it's not required, or this is > > a rather popular bug. > > I suspect it'll be playing under the assumption that going from "no > code" to "code" is fine since the icache is cold.
A previous trampoline would ruin that.
Fortunately, PowerPC is not as brain-dead as ARM and IA64. (not that I'm writing code for any of these) - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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