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    SubjectRe: [PATCH] [16/35] i386: Add an option for the VIA C7 which sets appropriate L1 cache
    On Sat, Apr 28, 2007 at 02:08:58PM -0400, Jeff Garzik wrote:
    > Andi Kleen wrote:
    > > From: Simon Arlott <simon@arlott.org>
    > >
    > > The VIA C7 is a 686 (with TSC) that supports MMX, SSE and SSE2, it also has
    > > a cache line length of 64 according to
    > > http://www.digit-life.com/articles2/cpu/rmma-via-c7.html. This patch sets
    > > gcc to -march=686 and select s the correct cache shift.
    > >
    > > Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
    > > Signed-off-by: Andi Kleen <ak@suse.de>
    > > Cc: Andi Kleen <ak@suse.de>
    > > Cc: Dave Jones <davej@codemonkey.org.uk>
    > > Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
    > > Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
    >
    > Has it been verified in the field that this CPU supports CMOV?

    Yes. All their CPUs for some time now have done so.

    Dave

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