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Subject[PATCH 4/10] smpboot: use safe_apic_wait_icr_idle - x86_64
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Date
The functionality provided by the new safe_apic_wait_icr_idle is being
open-coded all over "kernel/smpboot.c". Use safe_apic_wait_icr_idle
instead to consolidate code and ease maintenance.

Signed-off-by: Fernando Luis Vazquez Cao <fernando@oss.ntt.co.jp>
---

diff -urNp linux-2.6.21-rc7-orig/arch/x86_64/kernel/smpboot.c linux-2.6.21-rc7/arch/x86_64/kernel/smpboot.c
--- linux-2.6.21-rc7-orig/arch/x86_64/kernel/smpboot.c 2007-04-18 15:27:48.000000000 +0900
+++ linux-2.6.21-rc7/arch/x86_64/kernel/smpboot.c 2007-04-18 15:52:08.000000000 +0900
@@ -430,8 +430,8 @@ static void inquire_remote_apic(int apic
*/
static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip)
{
- unsigned long send_status = 0, accept_status = 0;
- int maxlvt, timeout, num_starts, j;
+ unsigned long send_status, accept_status = 0;
+ int maxlvt, num_starts, j;

Dprintk("Asserting INIT.\n");

@@ -447,12 +447,7 @@ static int __cpuinit wakeup_secondary_vi
| APIC_DM_INIT);

Dprintk("Waiting for send to finish...\n");
- timeout = 0;
- do {
- Dprintk("+");
- udelay(100);
- send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
- } while (send_status && (timeout++ < 1000));
+ send_status = safe_apic_wait_icr_idle();

mdelay(10);

@@ -465,12 +460,7 @@ static int __cpuinit wakeup_secondary_vi
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);

Dprintk("Waiting for send to finish...\n");
- timeout = 0;
- do {
- Dprintk("+");
- udelay(100);
- send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
- } while (send_status && (timeout++ < 1000));
+ send_status = safe_apic_wait_icr_idle();

mb();
atomic_set(&init_deasserted, 1);
@@ -509,12 +499,7 @@ static int __cpuinit wakeup_secondary_vi
Dprintk("Startup point 1.\n");

Dprintk("Waiting for send to finish...\n");
- timeout = 0;
- do {
- Dprintk("+");
- udelay(100);
- send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
- } while (send_status && (timeout++ < 1000));
+ send_status = safe_apic_wait_icr_idle();

/*
* Give the other CPU some time to accept the IPI.

-
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