[lkml]   [2007]   [Nov]   [4]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRe: [PATCH] fix i486 boot failure due to stale %ds
    On Sun, 04 Nov 2007 11:41:58 -0800, H. Peter Anvin wrote:
    > Mikael Pettersson wrote:
    > >
    > > First patch didn't build. Second patch builds and boots Ok.
    > >
    > > So this means the 486 DX4 has a buggy mov to %cr0?
    > >
    > Apparently.

    Maybe not. I had a look in Intel's SDM Vol3, and the
    section "switching to protected mode" specifies that
    a move to %cr0 that sets PE should immediately be
    followed by a far jmp or call. They write that "random
    failures can occur if other instructions exist between
    [the move to %cr0] and [the far jmp/call]". The current
    version of pmjump.S does exactly that: it executes
    a bunch of moves to segment registers in that window.

    (Section 9.9.1 in the Sept. 2005 revision I have in
    front of me.)

    Similarly, section "serializing instructions" writes
    that a move to %cr0 that enables or disables paging
    should be followed by a jump. They write that this isn't
    required in P4 or P6 family processors, but is required
    for compatibility with other ia32 processors. Reading
    between the lines, they imply that older ia32 processors
    don't treat %cr0 writes as completely serializing.

    (Section 7.4 in the Sept. 2005 revision.)

    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to
    More majordomo info at
    Please read the FAQ at

     \ /
      Last update: 2007-11-04 23:01    [W:0.018 / U:214.040 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site