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SubjectRe: [perfmon] Re: [perfmon2] perfmon2 merge news
On Wed, 14 Nov 2007 at 10:44 +0000, Will Cohen wrote:
> Andi Kleen wrote:
> >>One approach does not prevent the other. Assuming you allow cr4.pce, then
> >>nothing prevents
> >>a self-monitoring thread from reading the counters directly. You'll just
> >>get the
> >>lower 32-bit of it. So if you read frequently enough, you should not have
> >>a problem.
> >
> >Hmm? RDPMC is 64bit.
> There are a number of processors that have 32-bit counters such as the IBM
> power processors. On many x86 processors the upper bits of the counter are
> sign extended from the lower 32 bits. Thus, one can only assume the lower
> 32-bit are available. Roll over of values is quite possible (<2 seconds of
> cycle count), so additional work needs to be done to obtain a valid value.

On x86 they are sign-extended only on write, on read they are 40 bits wide
for intel, 48 bits for AMD.

BTW, isn't rdpmc only enable for ring 0 on linux ? I remember a patch
to disable it, dunno if it has been applied.


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