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SubjectRe: LFENCE instruction (was: [rfc][patch 3/3] x86: optimise barriers)
On Mon, 15 Oct 2007 22:47:42 +0200 (CEST)
Mikulas Patocka <> wrote:

> > According to latest memory ordering specification documents from
> > Intel and AMD, both manufacturers are committed to in-order loads
> > from cacheable memory for the x86 architecture. Hence, smp_rmb()
> > may be a simple barrier.
> >
> >
> >
> Hi
> I'm just wondering about one thing --- what is LFENCE instruction
> good for?
> SFENCE is for enforcing ordering in write-combining buffers (it
> doesn't have sense in write-back cache mode).
> MFENCE is for preventing of moving stores past loads.
> But what is LFENCE for? I read the above documents and they already
> say that CPUs have ordered loads.

The cpus also have an explicit set of instructions that deliberately do
unordered stores/loads, and s/lfence etc are mostly designed for those.
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