Messages in this thread |  | | Date | Fri, 8 Sep 2006 22:25:47 -0700 (PDT) | From | Christoph Lameter <> | Subject | Re: [PATCH] Fix longstanding load balancing bug in the scheduler. |
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On Fri, 8 Sep 2006, Siddha, Suresh B wrote:
> > One cacheline sized 128bytes will support all 1024 cpus that IA64 allows. > > cacheline align the cpumask? > > one or more, it is unnecessary for the common case.
The common case is an arch with much less cpus. The maxinum on i386 f.e. is 255 meaning 8 bytes. That fits in the cacheline that is already used for the stack frame of the calling function.
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