lkml.org 
[lkml]   [2006]   [Sep]   [9]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH] Fix longstanding load balancing bug in the scheduler.
On Fri, 8 Sep 2006, Siddha, Suresh B wrote:

> > One cacheline sized 128bytes will support all 1024 cpus that IA64 allows.
> > cacheline align the cpumask?
>
> one or more, it is unnecessary for the common case.

The common case is an arch with much less cpus. The maxinum on i386
f.e. is 255 meaning 8 bytes. That fits in the cacheline that is already
used for the stack frame of the calling function.

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2006-09-09 07:29    [W:0.053 / U:5.208 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site