Messages in this thread | | | Subject | Re: TG3 data corruption (TSO ?) | From | Alan Cox <> | Date | Sun, 10 Sep 2006 01:38:18 +0100 |
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Ar Sul, 2006-09-10 am 08:36 +1000, ysgrifennodd Benjamin Herrenschmidt: > Well, some of you (Alan, you, etc...) seem to imply that it's always > been the rule to have a memory store followed by an MMIO write be > strongly ordered.
It has always been the rule
> However, if you look at drivers like e1000, USB OHCI, or even sungem > (:-) they, all have at least wmb()'s between updating descriptor in
Driver hacks to cope with platform authors who got read/writel wrong.
> semantics. At least what is implemented currently on PowerPC is the > __raw_* versions which not only have no barriers at all (they don't even > order between MMIOs, for example, readl might cross writel), and do no > endian swap. Quite a mess of semantics if you ask me... Then there has
__writel/__readl seems more in keeping for just not locking.
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