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SubjectRe: question regarding cacheline size
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On Thu, 2006-09-07 at 06:40 -0600, Matthew Wilcox wrote:
> On Thu, Sep 07, 2006 at 02:33:25PM +0200, Arjan van de Ven wrote:
> >
> > >
> > > So I think we should redo the PCI subsystem to set cacheline size during
> > > the buswalk rather than waiting for drivers to ask for it to be set.
> >
> > ... while allowing for quirks for devices that go puke when this
> > register gets written ;)
> >
> > (afaik there are a few)
>
> So you want:
>
> unsigned int no_cls:1; /* Device pukes on write to Cacheline Size */
>
> in struct pci_dev?

something like that yes...


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