Messages in this thread | | | Date | Sat, 23 Sep 2006 21:28:21 -0400 | From | Dave Jones <> | Subject | Re: New Intel feature flags. |
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On Sun, Sep 24, 2006 at 03:21:06AM +0200, Michal Piotrowski wrote: > Hi Dave, > > On 24/09/06, Dave Jones <davej@redhat.com> wrote: > > Add supplemental SSE3 instructions flag, and Direct Cache Access flag. > > As described in "Intel Processor idenfication and the CPUID instruction > > AP485 Sept 2006" > > > > Signed-off-by: Dave Jones <davej@redhat.com> > > > > --- local-git/arch/i386/kernel/cpu/proc.c~ 2006-09-23 20:46:35.000000000 -0400 > > +++ local-git/arch/i386/kernel/cpu/proc.c 2006-09-23 20:48:02.000000000 -0400 > > @@ -46,8 +46,8 @@ static int show_cpuinfo(struct seq_file > > > > /* Intel-defined (#2) */ > > "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est", > > - "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL, > > - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, > > + "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL, > > ssse3? Typo?
No. It stands for Supplemental SSE3. SSE is already indicated by 'pni'.
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