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SubjectRe: Uses for memory barriers
Paul E. McKenney wrote:
> On Wed, Sep 20, 2006 at 04:48:45AM +1000, Nick Piggin wrote:
> Sooner or later, the cacheline comes to the store queue, defining
> the ordering. All changes that occurred in the store queue while
> waiting for the cache line appear to other CPUs as having happened
> in very quick succession while the cacheline resides with the store
> queue in question.
> So, what am I missing?

Maybe I'm missing something. But if the same CPU loads the value
before the store becomes visible to cache coherency, it might see
the value out of any order any of the other CPUs sees.

SUSE Labs, Novell Inc.
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