lkml.org 
[lkml]   [2006]   [Sep]   [19]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    Date
    From
    SubjectRe: Uses for memory barriers
    On Wed, Sep 20, 2006 at 03:51:29AM +1000, Nick Piggin wrote:
    > Alan Stern wrote:
    > >On Wed, 20 Sep 2006, Nick Piggin wrote:
    >
    > >>I don't think that need be the case if one of the CPUs that has written
    > >>the variable forwards the store to a subsequent load before it reaches
    > >>the cache coherency (I could be wrong here). So if that is the case, then
    > >>your above example would be correct.
    > >
    > >I don't understand your comment. Are you saying it's possible for two
    > >CPUs to observe the same two writes and see them occurring in opposite
    > >orders?
    >
    > If store forwarding is able to occur outside cache coherency protocol,
    > then I don't see why not. I would also be interested to know if this
    > is the case on real systems.

    We are discussing multiple writes to the same variable, correct?

    Just checking...

    Thanx, Paul
    -
    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to majordomo@vger.kernel.org
    More majordomo info at http://vger.kernel.org/majordomo-info.html
    Please read the FAQ at http://www.tux.org/lkml/

    \
     
     \ /
      Last update: 2006-09-19 20:21    [W:3.736 / U:0.336 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site