Messages in this thread | | | Date | Tue, 19 Sep 2006 11:19:20 -0700 | From | "Paul E. McKenney" <> | Subject | Re: Uses for memory barriers |
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On Wed, Sep 20, 2006 at 03:51:29AM +1000, Nick Piggin wrote: > Alan Stern wrote: > >On Wed, 20 Sep 2006, Nick Piggin wrote: > > >>I don't think that need be the case if one of the CPUs that has written > >>the variable forwards the store to a subsequent load before it reaches > >>the cache coherency (I could be wrong here). So if that is the case, then > >>your above example would be correct. > > > >I don't understand your comment. Are you saying it's possible for two > >CPUs to observe the same two writes and see them occurring in opposite > >orders? > > If store forwarding is able to occur outside cache coherency protocol, > then I don't see why not. I would also be interested to know if this > is the case on real systems.
We are discussing multiple writes to the same variable, correct?
Just checking...
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