lkml.org 
[lkml]   [2006]   [Aug]   [16]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    Date
    SubjectRe: [PATCH 1/2]: powerpc/cell spidernet bottom half
    From
    On Wed, Aug 16, 2006 at 02:32:03PM -0700, David Miller wrote:
    >
    > The best schemes seem to be to interrupt mitigate using a combination
    > of time and number of TX entries pending to be purged. This is what
    > most gigabit chips seem to offer.

    I seem to be having a multi-hour delay for email delivery, so maybe
    we've crossed emails.

    A "low watermark interrupt" is an interrupt that is generated when
    some queue is "almost empty". This last set of patches implement this
    for the TX queue. The interrupt pops when 3/4ths of the packets
    in the queue have been processed. Playing with ths setting
    (3/4ths or some other number) seemed to make little difference.

    > On Tigon3, for example, we tell the chip to interrupt if either 53
    > frames or 150usecs have passed since the first TX packet has become
    > available for reclaim.

    The nature of a low-watermark interrupt is that it NEVER pops, as long
    as the kernel keeps putting more stuff into the queue, so as to keep
    the queue at least 1/4'th full. I don't know how to mitigate interrupts
    more than that.

    --linas
    -
    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to majordomo@vger.kernel.org
    More majordomo info at http://vger.kernel.org/majordomo-info.html
    Please read the FAQ at http://www.tux.org/lkml/

    \
     
     \ /
      Last update: 2006-08-17 01:27    [W:0.024 / U:31.856 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site