Messages in this thread Patch in this message | | | Date | Sat, 29 Jul 2006 21:42:37 +0200 | From | "Andi Kleen" <> | Subject | [PATCH for 2.6.18] [2/8] x86_64: On Intel systems when CPU has C3 don't use TSC |
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On Intel systems generally the TSC stops in C3 or deeper, so don't use it there. Follows similar logic on i386.
This should fix problems on Meroms.
Signed-off-by: Andi Kleen <ak@suse.de>
--- arch/x86_64/kernel/time.c | 16 ++++++++++++---- 1 files changed, 12 insertions(+), 4 deletions(-)
Index: linux-2.6.18-rc2-git7/arch/x86_64/kernel/time.c =================================================================== --- linux-2.6.18-rc2-git7.orig/arch/x86_64/kernel/time.c +++ linux-2.6.18-rc2-git7/arch/x86_64/kernel/time.c @@ -28,6 +28,7 @@ #include <linux/acpi.h> #ifdef CONFIG_ACPI #include <acpi/achware.h> /* for PM timer frequency */ +#include <acpi/acpi_bus.h> #endif #include <asm/8253pit.h> #include <asm/pgtable.h> @@ -953,11 +954,18 @@ __cpuinit int unsynchronized_tsc(void) #ifdef CONFIG_SMP if (apic_is_clustered_box()) return 1; - /* Intel systems are normally all synchronized. Exceptions - are handled in the check above. */ - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) - return 0; #endif + /* Most intel systems have synchronized TSCs except for + multi node systems */ + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { +#ifdef CONFIG_ACPI + /* But TSC doesn't tick in C3 so don't use it there */ + if (acpi_fadt.length > 0 && acpi_fadt.plvl3_lat < 100) + return 1; +#endif + return 0; + } + /* Assume multi socket systems are not synchronized */ return num_present_cpus() > 1; } - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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