Messages in this thread | | | From | Andi Kleen <> | Subject | Re: [discuss] Re: [PATCH] Allow all Opteron processors to change pstate at same time | Date | Wed, 26 Jul 2006 18:54:20 +0200 |
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> AMD Opteron(tm) Processor 838 stepping 01 > CPU 3: Syncing TSC to CPU 0. > CPU 3: synchronized TSC with CPU 0 (last diff -109 cycles, maxerr 1024
Hmm, indeed - i would have expected higher max errors too. It should have worked in theory. No explanation currently.
> cycles) > powernow-k8: 0 : fid 0xe (2200 MHz), vid 0x6 > powernow-k8: 1 : fid 0xc (2000 MHz), vid 0x8 > powernow-k8: 2 : fid 0xa (1800 MHz), vid 0xa > powernow-k8: 3 : fid 0x2 (1000 MHz), vid 0x12 > > Is there a better test we can be using?
I don't know of any. Ok I guess it would be possible to write something in user space, but it would likely look similar to the algorithm the kernel uses.
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