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SubjectRe: REGRESSION: the new i386 timer code fails to sync CPUs
On Sun, 23 Jul 2006 14:08:29 +0200
Matthias Urlichs <smurf@smurf.noris.de> wrote:

> Hi,
>
> Andrew Morton:
> > - CPU0 and CPU1 share a TSC and CPU2 and CPU3 share another TSC.
> >
> That mmakes sense, since they're one dual-core Xeon each.

OK.

> > - Earlier kernels didn't use the TSC as a time source whereas this one
> > does, hence the problems which you're observing.
> >
> Correct; see below.
>
> > I assume that booting with clock=pit or clock=pmtmr fixes it?
> >
> Testing... yes, both.
>
> > It would be useful to check your 2.6.17 boot logs, see if we can work out
> > what 2.6.17 was using for a clock source.
> >
> That's easy:
>
> 2.6.17 -Using pmtmr for high-res timesource
> 2.6.18git +Time: tsc clocksource has been installed.
>
> I missed those two lines, as in the boot logs they're not really
> adjacent, so they got lost in the jumble of other differences.

OK, thanks. Marking the TSC as bad in this case is simple to do - let us
let John work out the best way.

We must have lost a TSC sanity check somewhere along the way. I wonder
what it was?

> Interestingly, CPU0/1 gets 6000 bogomips while CPU2/3 only reaches 5600 ..?
> (That happens with both kernels.) I do wonder why, and whether this has any
> bearing on the current problem.

I wouldn't expect it to matter, unless the TSCs are running at different
speeds or something.

Also the sched-domain migration costs are grossly different between the two
kernels. Maybe we changed the migration-cost-estimation code; I forget.

I'll see if we can get an expert opinion on the write_tsc() failure.
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