Messages in this thread | | | From | Andi Kleen <> | Subject | Re: [PATCH 01/14] Per zone counter functionality | Date | Fri, 9 Jun 2006 06:38:28 +0200 |
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On Friday 09 June 2006 06:00, Andrew Morton wrote: > On Thu, 8 Jun 2006 16:02:44 -0700 (PDT) > Christoph Lameter <clameter@sgi.com> wrote: > > > Per zone counter infrastructure > > > > Is the use of 8-bit accumulators more efficient than using 32-bit ones? > Obviously it's better from a cache POV, given that we have a pretty large > array of them. But is there a downside on some architectures in not using > the natural wordsize?
Maybe on very old alphas which didn't have 8 bit stores. They need a RMW cycle.
Other than that i wouldn't expect any problems. RISCs will just do the usual 32bit add in registers, but do a 8bit load/store.
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