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Subject[PATCHSET] block: fix PIO cache coherency bug, take 2
Hello, all.

Here's another round of block PIO cache coherency fix patchset. The
previous try[1] was rejected because flush_dcache_page() was excessive
and couldn't be called from irq context. A new cachetlb interface has
been introduced - flush_kernel_dcache_page(), which is only
responsible for flushing the kernel mapping and safe to call from irq
context. The function is implemented only for parisc. This patchset
adds implementation for arm.

blk kmap wrappers have been dropped and calls to
flush_kernel_dcache_page() have been directly added. Because
flush_kernel_dcache_page() hasn't been implemented on many
architectures, converting to such wrappers breaks cache coherency for
such architectures. kmap should be updated after all archtectures
with aliasing caches implement flush_kernel_dcache_page().

Russell, can you please verify arm's flush_kernel_dcache_page()? I
tried to implement flush_anon_page() too but didn't know what to do
with anon_vma object. It seems that a call to
__cpuc_flush_user_range() should do the job but it requires
vma->vm_flags to see whether it's an executable page. To access vma
from anon mapped page, page->mapping:anon_vma->lock should be grabbed
and probably the first vma on the list can be used, which is kind of
complex. I think the options here are...

* adding vma argument to flush_anon_page()
* always flush for the worst vm_flags

I have only compile tested. Please verify this fixes the coherency
problem on arm.

Jens, if everyone is happy with this, can you push this patchset
through blk tree? As this change only adds calls to
flush_kernel_dcache_page() which is currently implement only on parisc
and arm, I think including this fix into 2.6.17 shouldn't cause too
much trouble.




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