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    SubjectRe: [PATCH] Document Linux's memory barriers [try #2]
    On Wed, Mar 08, 2006 at 11:26:41AM -0800, Linus Torvalds wrote:
    > > I presume there only needs to be an mmiowb() here if you've got the
    > > appropriate CPU's I/O memory window set up to be weakly ordered.
    >
    > Actually, since the different NUMA things may have different paths to the
    > PCI thing, I don't think even the mmiowb() will really help. It has
    > nothing to serialize _with_.
    >
    > It only orders mmio from within _one_ CPU and "path" to the destination.
    > The IO might be posted somewhere on a PCI bridge, and and depending on the
    > posting rules, the mmiowb() just isn't relevant for IO coming through
    > another path.

    Looking at the SGI implementation, it's smarter than you think. Looks
    like there's a register in the local I/O hub that lets you determine
    when this write has been queued in the appropriate host->pci bridge.
    So by the time __sn_mmiowb() returns, you're guaranteed no other CPU
    can bypass the write because the write's got far enough.

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