[lkml]   [2006]   [Mar]   [30]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRE: Synchronizing Bit operations V2
    On Thu, 30 Mar 2006, Chen, Kenneth W wrote:

    > Christoph Lameter wrote on Thursday, March 30, 2006 6:38 PM
    > > > > Neither one is correct because there will always be one combination of
    > > > > clear_bit with these macros that does not generate the required memory
    > > > > barrier.
    > > >
    > > > Can you give an example? Which combination?
    > >
    > > For Option(1)
    > >
    > > smp_mb__before_clear_bit()
    > > clear_bit(...)(
    > Sorry, you totally lost me. It could me I'm extremely slow today. For
    > option (1), on ia64, clear_bit has release semantic already. The comb
    > of __before_clear_bit + clear_bit provides the required ordering. Did
    > I miss something? By the way, we are talking about detail implementation
    > on one specific architecture. Not some generic concept that clear_bit
    > has no ordering stuff in there.

    We are talking about IA64 and IA64 only generates an single instruction
    with either release or acquire semantics for the case in which either
    smb_mb__before/after_clear_bit does nothing.

    Neither acquire nor release is a memory barrier on IA64.

    The combination of both does the equivalent but then we do not have both
    acquire and release if either smb_mb__before/after_clear bit does

    For clear_bit you have both uses in the kernel




    clear_bit() in itself does not have barrier semantics on IA64. Therefore
    smb_mb_after and before must both provide a memory barrier.

    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to
    More majordomo info at
    Please read the FAQ at

     \ /
      Last update: 2006-03-31 05:04    [W:0.030 / U:2.640 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site