Messages in this thread | | | Date | Fri, 10 Mar 2006 19:19:51 -0600 | From | Robert Hancock <> | Subject | Re: Memory barriers and spin_unlock safety |
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Linus Torvalds wrote: > Close, yes. HOWEVER, it's only really ordered wrt the "innermost" bus. I > don't think PCI bridges are supposed to post PIO writes, but a x86 CPU > basically won't stall for them forever. I _think_ they'll wait for it to > hit that external bus, though.
PCI I/O writes are allowed to be posted by the host bus bridge (not other bridges) according to the PCI 2.2 spec. Maybe no x86 platform actually does this, but it's allowed, so technically a device would need to do a read in order to ensure that I/O writes have arrived at the device as well.
-- Robert Hancock Saskatoon, SK, Canada To email, remove "nospam" from hancockr@nospamshaw.ca Home Page: http://www.roberthancock.com/
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