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SubjectRe: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch doesn't support it
On Wed, Dec 06, 2006 at 11:16:55AM -0800, Christoph Lameter wrote:

> But then its also just requires disable/enable interrupts on UP which may
> be cheaper than an atomic operation.
> > For CPUs with load locked + store conditional, it is expensive.
> Because it locks the bus? I am not that familiar with those architectures
> but it seems that those will have a general problem anyways.

On a decent implementation ll/sc will have the same cost as ordinary
non-atomic load and store instructions. A likely uniprocessor
implementation uses a single flip-flop ("llbit") in the CPU which is set
by ll and cleared by any exception handler, especially interrupt. A later
store conditional will then simply fail if that bit is cleared. That
is extremly trivial stuff. On SMP it's somewhat more complex; A
processor will have to remember the address used with ll and start
snooping the bus for writes to it. The store conditional will then
go and upgrade the cache line to exclusive state if the llbit is still
set and perform the store. The llbit would be cleared if the processor
has snooped any other write to the cacheline. Details are fun but that's
bascially how it's implemented.

Of course load linked / store conditional are typically used in loops
so there is a little extra overhead from that especially where when the
branch is misspredicted.

Also note there is no locked cycle required to implement load linked /
store conditional.

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