[lkml]   [2006]   [Nov]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH] ALSA: hda-intel - Disable MSI support by default
>> However, they have to do all the work of processing the memory
>> transation that the MSI is on the PCI bus, I don't think they
>> would go
>> so far out of their way to reorder things even if they converted the
>> MSI packet into a PIN to the APIC, for example.
> That would suck and not surprise me that much in fact... Take the
> Apple
> bridge... it's unclear at which point they actually decode the MSI and
> HT interrupts (the later are just internally converted to MSI-like
> stores) to turn them into toggling of MPIC lines,

That's all documented just fine.

> but it probably
> happens as an MMIO slave on the main xbar

Yes indeed.

> and I'm not 100% certain it
> provides ordering vs. the previous stores to memory as they are in the
> coherent domain and the MMIO is not. I just hope very much :-)

All those DMA stores get reflected to the CPUs (the north
bridge itself doesn't keep a cache directory). All this
happens in-order. There probably _is_ a window where the
last DMA store isn't yet globally visible but the CPU
interrupt was already signaled, but the act of trying to
access that data orders it itself :-)

> Because
> the store queue to memory can re-order on U4.

That's only the store queue to the actual memory devices,
it's outside of the coherent domain anyway.


To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to
More majordomo info at
Please read the FAQ at

 \ /
  Last update: 2006-11-15 11:09    [W:0.065 / U:10.136 seconds]
©2003-2018 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site